A digital-to-analog converter (DAC) converts a digital input signal to an analog output signal. The digital input signal is represented by N-bits each of which is set to one of two states (0 or 1). The analog output signal can have any value in a continuous range.
The performance of the DAC is based on linearity and accuracy. Linearity of the DAC is a measure of the precision of the conversion. In an ideal DAC, equal increments in the digital input correspond to equal increments in the analog output value. For example, for a DAC having a 3-bit digital input signal, there are (23)=8 increments. Thus, with a range of 1V, the output voltage should change by xe2x85x9V for each one bit change in the digital input signal. Linearity errors contribute to the accuracy of the converter, that is, the difference between the actual analog voltage and the ideal analog voltage.
FIG. 1 is a block diagram of a prior art switched capacitor digital-to-analog converter (xe2x80x9cDACxe2x80x9d) 100. The DAC includes a switch capacitor array 102, a sampling capacitor 104 and a charge-to-voltage buffer 106.
The DAC receives a digital input that can be represented by a set of N bits {b0 b1 b2 . . . bNxe2x88x921}. The least significant bit (LSB) of the digital input is represented by b0 and the most significant bit (MSB) is represented by bNxe2x88x921. Vref1 and Vref2 are two reference (DC) voltage levels.
The switch capacitor array 102 includes an initializing cell and a cell for each bit in the digital input bNxe2x88x921-b0. The state (0 or 1) of a bit of the digital input charges a capacitor in the respective cell in the switch capacitor array 102 to one of two reference voltages Vref1, Vref2. Switches, driven by a non-overlapping three phase clock ("PHgr"1, "PHgr"2, "PHgr"3), force charge to move through the cells in the switch capacitor array from the cell corresponding to the least significant bit (b0) of the digital input to the cell corresponding to the most significant bit (bnxe2x88x921). The accumulated charge of the capacitor corresponding to the most significant bit of the digital input corresponds to the final charge. This accumulated charge is sampled by the sampling capacitor 104 and converted to an output voltage Vout by the charge-to-voltage buffer 106.
FIG. 2 is a circuit diagram of the prior art switch capacitor array circuit 100 shown in FIG. 1. A non-overlapping three-phase clock ("PHgr"1, "PHgr"2, "PHgr"3) controls the operation of the DAC. Each switch is labeled with the phase of the clock that controls the switch. The switch is closed during the controlling phase.
Three switch capacitor cells of the switch capacitor array 102 and the initializing cell are shown. The initializing cell includes a charge switch Sc, a transfer switch ST and an initializing capacitor Ci. Each switch capacitor cell includes a capacitor C and three switches (a charge switch SC, a reference switch SR and a transfer switch ST). The reference switch SR is set to one of the two reference voltages (Vref1, Vref2) dependent on the state of the respective bit of the digital input.
Each switch capacitor cell is charged to the selected reference voltage while the charge switch Sc is closed. The stored charge is transferred to the next most significant switch capacitor cell in the array while the transfer switch ST is closed.
Referring to the switch capacitor cell for the Least Significant bit (LSB) b0, during phase "PHgr"1, the charge switch in the b0 cell is closed to charge the capacitor C to Vref1 or Vref1, depending on the value of b0 and thus the state of switch SR. In the example shown, bo=1, so capacitor C is charged to Vref1. During phase "PHgr"2, the transfer switch in the initializing cell is closed to transfer the charge stored in the initializing capacitor to the b0 cell. During phase "PHgr"3, the transfer switch in the b0 cell is closed to transfer the combined charge (initializing cell and b0 cell) to the switch capacitor cell for the next significant bit, bl. Thus, the charge is accumulated by combining charge from adjacent cells and transferring the accumulated charge to the cell corresponding to the next most significant bit.
The charge-to-voltage buffer 106 is a differential amplifier 200 configured in single-ended mode with capacitor feedback CF between the inverting input and the output. During phase "PHgr"2, the charge switch SC for the sampling capacitor Cs is closed, the sampling capacitor CS is pre-charged to Vref1 while the differential amplifier holds the prior output voltage. During phase "PHgr"3, the charge stored in the MSB switch capacitor cell and the charge resulting from the digital-to-analog conversion is shared with the fixed charge stored in the sampling capacitor CS. The sampling capacitor CS is not connected to the differential amplifier. Also, during phase "PHgr"3, a path to ground is provided from the non-inverting input of the differential amplifier through switch SG and the feedback CF capacitor is reset, yielding a zero output voltage Vout. Finally, during phase "PHgr"1 the charge stored into the sampling capacitor CS is transferred into the feedback capacitor CF.
The linearity of the DAC is limited by mismatch in the capacitors in each cell in the switch capacitor array, stray capacitance and the slew-rate performance of the differential amplifier.
Any mismatch in the capacitors in each cell affects the charge redistribution phase between adjacent cells and thus affects the linearity. To limit linearity problems due to mismatch in capacitors, the sampling capacitor must be selected so that the same loading and neighboring conditions present in other cells of the capacitor array are recreated for the last (MSB) cell, before the amplification is performed. Also, stray capacitance in parallel with the sampling capacitor is introduced by the switch Sc connected to the sampling capacitor. The value of this stray capacitance is dependent on the voltage Vin across the sampling capacitor CS at the end of phase "PHgr"3.
The charge sharing between the sampling capacitor CS and the capacitor C in the MSB cell halves the final voltage to be amplified. This reduces the signal-to-noise ratio of the output voltage by 3 dB compared to the case in which there is no voltage reduction.
The slew rate of a differential amplifier is the maximum rate of output voltage change which is the maximum charging current divided by the capacitance. The differential amplifier output and the feedback capacitors are always reset to zero during phase "PHgr"3. Therefore, the output voltage swings from zero up to the converted value during phase "PHgr"1 and then back down to zero during phase "PHgr"3. Thus, the output of the differential amplifier is slew rate limited during phase "PHgr"1. The slew rate introduces harmonic distortion in the analog output spectrum.
A digital to analog converter with high linearity, low slew rate and high signal to noise ratio is presented. The digital to analog converter includes a capacitor array removably coupled to a switched capacitor amplifier. The result of the digital analog conversion in the capacitor array is provided directly to the amplifier from the capacitor in the cell corresponding to the most significant bit in the capacitor cell. This results in a high signal to noise ratio because the result of the conversion is not halved. The slew rate is reduced through the use of a memory capacitor which provides the initial output voltage and stores the output voltage while a feedback capacitor is reset.
The digital to analog converter includes a capacitor array and a switched capacitor amplifier. The switched capacitor amplifier includes a feedback capacitor; and a memory capacitor removably coupled to the output of the capacitor array. The output of the memory capacitor is charged to the output voltage of the capacitor array. The memory capacitor stores the output voltage while the feedback capacitor is reset and the memory capacitor provides the initial output voltage when coupled to the capacitor array.
The capacitor array includes a cell for each bit in a digital input signal, each cell includes a cell capacitor. The cell capacitor in the cell corresponding to the most significant bit of the digital input is removably coupled to the feedback capacitor and the memory capacitor in the switched capacitor array to charge the feedback capacitor and the memory capacitor to the converted value.
Stray capacitance is discharged by removably coupling the cell capacitor in the most significant bit cell to ground. The feedback capacitor is discharged by coupling both plates of the feedback capacitor to ground.
Further improvement in linearity may be achieved by including a pair of switches in parallel between the bottom plate of each cell capacitor and ground to provide loading conditions substantially matching the cell corresponding to the most significant bit. One of the switches is held open and the other switch is held closed.
A pair of switches may also be added to an initializing cell in the capacitor to further increase linearity, the pair of switches are coupled in parallel between the bottom plate of the initializing capacitor and ground. Another switch may be coupled between the top plate of the initializing capacitor and ground.